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Browse Prior Art Database

Low Sheet Resistance Gate Electrode With Conventional Borderless Contacts

IP.com Disclosure Number: IPCOM000037071D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Cronin, JE: AUTHOR [+4]

Abstract

By strapping doped polysilicon with titanium (Ti) and aluminum (Al) after high temperature gate electrode processing, gate electrodes having low electrical resistance are formed. Aluminum oxide etch stop layers are used to achieve borderless contacts.

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Low Sheet Resistance Gate Electrode With Conventional Borderless Contacts

By strapping doped polysilicon with titanium (Ti) and aluminum (Al) after high temperature gate electrode processing, gate electrodes having low electrical resistance are formed. Aluminum oxide etch stop layers are used to achieve borderless contacts.

Referring to Fig. 1, gate oxide 2 is grown on silicon substrate 4. Polysilicon 6 is deposited and standard complementary metal oxide silicon (CMOS) process steps of block masking to implant P type impurity in polysilicon 6 in P type transistor areas and N impurity in N transistor areas are performed. Silicon nitride (Si3N4) 8 is then deposited. Gate electrodes are defined by etching through nitride 8 and polysilicon 6. Then, an oxide 3 is grown on the sidewalls of polysilicon 6. Sidewall spacers 9 are formed by depositing a conformal layer of Si3N4 and using an anisotropic etch to remove Si3N4 from all horizontal surfaces. Silicide contacts 12 and ion-implanted junctions 14 are then formed by standard processing. Aluminum oxide (Al2O3) 16 is then deposited. Silicon dioxide (SiO2) 18 is deposited and planarized to expose Si3N4 8 to complete the structure shown in Fig. 1.

Referring to Fig. 2, Si3N4 is selectively removed by RIE until polysilicon 6 is completely exposed. Then, Si3N4 is deposited and planarized by RIE to create sidewalls 20. Next, Ti and Al 22 are vacuum deposited. Si3N4 24 is next deposited to an overfill level and etched back be...