Browse Prior Art Database

Process for Forming a High-Aspect-Ratio Solder Interconnection

IP.com Disclosure Number: IPCOM000037094D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 109K

Publishing Venue

IBM

Related People

Greer, SE: AUTHOR [+3]

Abstract

A process is described for fabricating tall columns of deposited solder on chips or substrates to create non-reflowed and fatigue-resistant solder interconnections, and allow for direct chip attachment (DCA) applications.

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Process for Forming a High-Aspect-Ratio Solder Interconnection

A process is described for fabricating tall columns of deposited solder on chips or substrates to create non-reflowed and fatigue-resistant solder interconnections, and allow for direct chip attachment (DCA) applications.

Current moly mask solder deposition methods used to fabricate solder column interconnections limit column height to approximately the thickness of the mask. A new technique for forming high-aspect-ratio solder columns utilizes two masks in combination with reduced temperature depositions during selected portions of the process.

The new method creates nearly vertical columns of lead/tin (Pb/Sn) solder in the 12-mil high range on wafers or substrates. The first mask step is used to create approximately 50% of the solder column height while at the same time forming a series of stand-off bumps on which the second mask may rest during the balance of the solder column deposition

Referring to Fig. 1, a chrome, copper, gold and tin (Cr-Cu-Au-Sn) film approximately 10K angstroms thick is deposited through a moly mask onto a wafer substrate. Next a pure lead deposition approximately 6 mils thick is made through the same mask while using reduced deposition temperatures during the early phase to minimize halo formation. Note that the first mask has additional holes used to form stand-off bumps for the second mask step.

Referring to Fig. 2, the first mask is removed and a second mask (without bum...