Browse Prior Art Database

Delay Scaling

IP.com Disclosure Number: IPCOM000037112D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 4 page(s) / 84K

Publishing Venue

IBM

Related People

Chao, HH: AUTHOR [+3]

Abstract

This article describes a method for quickly and uniformly changing delay and tolerance information in a timing analysis database to reflect new technologies or technology enhancements.

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Delay Scaling

This article describes a method for quickly and uniformly changing delay and tolerance information in a timing analysis database to reflect new technologies or technology enhancements.

The present methodology for timing analysis consists of three main steps: delay generation, model build and trace. During the generation of a delay file, the logical and physical structure of the design is first expanded into its lower level form. Delay information is then generated for each AND/OR block through the use of a circuit timing model and a delay rule. For connections not on the chip level, delay is generated using off-chip delay calculation rules. It is in the on-chip and off-chip delay rules where the technology dependent delay and tolerance coefficients are stored.

The creation of the timing model is next done in model build. All the necessary delay files are gathered along with control information to produce the timing model itself. The resulting model file contains information about each pin in the model and delay information about each component of the model. It is the timing model which is modified during the delay scaling process.

The final step consists of the model trace where the previously created timing model file is used. The trace process first loads and levels the timing model. Next, the trace algorithm is used to trace forward and backward in the logic to produce arrival times and slacks, respectively. Slack is defined as the time difference between when a signal should arrive and when it actually arrives in the logic, giving a measure of path length as compared to a particular machine cycle time. It is this report which is used to analyze the design against the timing objectives of the machine.

The delay scaling programs aid the user in quickly making delay and tolerance modifications to the already existing timing model to explore the "what if" questions of the new design. It is particularly useful in analyzing the effect of new technologies on an existing design to check if design objectives could be met with a different technology.

Following is a description of the delay adjust programs themselves and how they interact with the already existing timing database.

Delay and tolerance modifications can be made on crucial parts of the design. These include: internal circuits on chip, off-chip driver circuits, array chips and off-chip package connections. The range in which a parameter can be scaled is from zero to one thousand percent. Below is a sample control statement input to the delay scaling program, w...