Browse Prior Art Database

SET/RESET System With Slow SET and Fast RESET

IP.com Disclosure Number: IPCOM000037114D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Le Pennec, JF: AUTHOR [+2]

Abstract

Disclosed is a circuit that performs a SET/RESET function with priority to RESET, SET being generated by a slow process (typically, a DTE application) and RESET being generated by a fast process (typically, a microprocessor application). The circuit has been sucessfully implemented on a CMOS gate-array showing a significant size improvement over existing equivalent designs, with no AC performance impact.

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SET/RESET System With Slow SET and Fast RESET

Disclosed is a circuit that performs a SET/RESET function with priority to RESET, SET being generated by a slow process (typically, a DTE application) and RESET being generated by a fast process (typically, a microprocessor application). The circuit has been sucessfully implemented on a CMOS gate- array showing a significant size improvement over existing equivalent designs, with no AC performance impact.

In an interfacing logic between slow frequency processes (a few KHz) and fast frequency processes (a few MGHz) with no phase relation between the two frequencies, there is often the need for a system monitoring the interrupts SET by the slow process, and the read and RESET of these interrupts by the fast process. The following design was achieved:

Latch 2 is positioned on the falling edge of a slow clock by a valid SET. OUT is then set to one if RESET is not active. When RESET becomes active, latch 1 as well as OUT are at zero. The loop between the inverted output of latch 2 and the ORed input of latch 1 puts the system back to its original state.

It is noticeable that under minor symmetrical design changes, the same concept can be applied to a circuit with dominant SET, or with a SET being generated by a fast process and a RESET being generated by a slow process.

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