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Selective Differential Delay Generator With Half Nanosecond Steps

IP.com Disclosure Number: IPCOM000037120D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Erdelyi, CK: AUTHOR [+4]

Abstract

One-input, two-output circuit blocks of identical construction are assembled in an array resulting in multiple outputs, each output having been delayed a predictable amount of time different from all other outputs. With the circuit implementation described, output delays are different by 1/2 nanosecond increments 20%.

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Selective Differential Delay Generator With Half Nanosecond Steps

One-input, two-output circuit blocks of identical construction are assembled in an array resulting in multiple outputs, each output having been delayed a predictable amount of time different from all other outputs. With the circuit implementation described, output delays are different by 1/2 nanosecond increments 20%.

An assembly of one-input, two-output circuit blocks are shown in Fig. 1. Each circuit block provides a delay T to one output and a delay T plus an incremental delay t to a second output. Thus a tree circuit of N stages provides outputs delayed from input time by times ranging from N(T) to N(T+t) in increments of time t.

One such circuit block is shown in detail in Fig. 2. This circuit block is capable of providing t = 1/2 nanosecond 20%. The circuit block is comprised of two parallel circuits each having four stages (A, B, C, and D); each stage contains a pair of field-effect transistors (FETs), one P-type and one N-type. The first stage A and the last stage C of the parallel circuits are of identical construction. Stage A is to buffer the input signal and stage D is to buffer the delay to the output to result in sharp, symmetrical rise and fall times. Stage B and C device dimensions are varied in the two parallel circuits to create the difference in delay t between the two circuits. Resistors R reduce effects of threshold variations of the transistors on delay time and provide added...