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Optimized Incremental Delay Generator

IP.com Disclosure Number: IPCOM000037125D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Erdelyi, CK: AUTHOR [+3]

Abstract

Two-input, single-output circuit blocks, e.g., OR circuits, of nearly identical construction are assembled in an array, resulting in an output having been delayed an amount of time dependent on the input addressed. Thus different delays in predictable increments are available from the data paths constructed. Such circuit capability is utilized when writing data on a storage disk, for instance. (Image Omitted)

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Optimized Incremental Delay Generator

Two-input, single-output circuit blocks, e.g., OR circuits, of nearly identical construction are assembled in an array, resulting in an output having been delayed an amount of time dependent on the input addressed. Thus different delays in predictable increments are available from the data paths constructed. Such circuit capability is utilized when writing data on a storage disk, for instance.

(Image Omitted)

Fig. 1 shows a series of two-input, one-output circuit blocks assembled into a tree having n inputs and a single output after going through k stages, where n = 2k . Time delay of an internal circuit addressed by one input to each of the circuit blocks is time T and the circuit addressed by a second input has a delay of T+t for first stage circuit blocks, T+2t for second stage, and so on to T+2(k-1)t in the last of k stages. Output timing varies then from kT to [kT + (n-1)t], relative to input pulse timing. Note that only one input is active at any time. This approach minimizes the number of circuit blocks required and is most useful for conservation of silicon area where numbers of delay paths are required.

Fig. 2 is an example of a circuit block which may be constructed to fulfill the requirements stated above. The circuit is an inverted OR (or NOR) gate, in which delay of circuit path 1 to OUT is determined by the dimensions of devices T1, T2, T7, and T8. Delay in circuit path 2 to OUT is determined by the dimensions o...