Browse Prior Art Database

Frequency Measurement Logic

IP.com Disclosure Number: IPCOM000037149D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

Hanna, CA: AUTHOR [+2]

Abstract

Disclosed is a means for determining the frequency of a pulsed or continuous-wave RF signal digitally by counting the transitions of the signal and a high-speed reference clock within a measurement time interval.

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Frequency Measurement Logic

Disclosed is a means for determining the frequency of a pulsed or continuous-wave RF signal digitally by counting the transitions of the signal and a high-speed reference clock within a measurement time interval.

A typical embodiment of the frequency measurement logic (FML) is shown in the figure. Two signal RF inputs are provided, selectable by a control line, and one reference RF input. Counters 2 and 4 count the SIGNAL transitions, and counters 3 and 5 count the REFERENCE transitions. Two sets of counters are provided, so that while one set is counting, the other set is settling, transferring the count to the output register, and resetting. Controls include a TRIGGER clock input, MODE select, INTERVAL input, and DATA VALID output.

Timing logic 1 is used to select either SIGNAL 1 or SIGNAL 2 inputs as controlled by the SIGNAL SELECT input. It generates the clock and reset signals for counters 2, 3, 4, and 5 depending on the mode (continuous or triggered) selected by the MODE input. It produces the control for multiplexers 6 and 7 and the clocks for output registers 8 and 9 to transfer stable counts to the output registers. It generates a DATA VALID output when valid counts are contained in output registers 8 and 9.

Triggered mode is used when frequency measurement is to begin at a particular event, such as when a radar pulse crosses the detection threshold. When in triggered mode, the FML holds counters 4 and 5 reset while the TRIGGER input is low. When the TRIGGER goes high, the FML waits for the next low-to-high transition of the SIGNAL input, and then begins counting transitions of both the SIGNAL and REFERENCE inputs in counters 4 and 5, respectively. It counts until the number of reference transitions indicated by the INTERVAL input have occurred (as determined by comparator 10), waits for the next low-to-high transitions of the SIGNAL input, and then stops both counters. It then transfers the contents of counter 4 to output register 8 through multiplexed 6, and counter 5 through multiplexer 7 to output register 9, resets counters 4 and 5, and repe...