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Write-Protection Mechanism for Nonvolatile Random-Access Memory

IP.com Disclosure Number: IPCOM000037160D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 60K

Publishing Venue

IBM

Related People

Stopyro, JW: AUTHOR

Abstract

Microprocessors in use today can address vast memory spaces due to large numbers of address bits. For example, the Motorola 68000 has 24 address bits giving it an address space of 8 megabytes. In many current small systems, or microprocessor-driven subsystems much of this addressibility is extraneous. In addition to some memory, the typical design will contain several other chips to provide the other required function. Typically, these chips will each contain several registers which will be memory mapped. To save chip level I/Os it is convenient to partition the address range into several functions. Logic is included to decode pertinent address bits to generate chip selects. In this way each chip will look only at one chip select and the required low level address bits.

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Write-Protection Mechanism for Nonvolatile Random-Access Memory

Microprocessors in use today can address vast memory spaces due to large numbers of address bits. For example, the Motorola 68000 has 24 address bits giving it an address space of 8 megabytes. In many current small systems, or microprocessor-driven subsystems much of this addressibility is extraneous. In addition to some memory, the typical design will contain several other chips to provide the other required function. Typically, these chips will each contain several registers which will be memory mapped. To save chip level I/Os it is convenient to partition the address range into several functions. Logic is included to decode pertinent address bits to generate chip selects. In this way each chip will look only at one chip select and the required low level address bits. For example, a chip with 4 registers will need 2 address bits and a chip select to determine which registers will be accessed when. This is in contrast to the 24 address bits needed if the partitioned address space approach is not adopted. Some chips may place constraints on accessing entities that reside in their address space. Since many of the address bits will not be functionally used in all address spaces, unused address bits may be used to design a hardware interlock mechanism to prevent accidental or unauthorized access to certain information. (See Fig. 1.)

A system or subsystem may need to keep information around between successive power on cycles. This might be IPL information or security information. However, it is convenient to be able to update this information without hardware changes. Such an architecture feature would be a good candidate for some type of hardware interlock mechanism to prevent inadvertent and unintentional modification of such information. A fairly rigorous sequential software routine, combined with the correct hardware support, could provide this protection. This information could be stored in a Non-Volatile memory, such as a Non-Volatile RAM (NVRAM).

The NVRAM physically contains two separate memory elements: a RAM and an EEPROM (Electrically Erasable PROM). The RAM area is directly accessible by the microprocessor. The EEPROM area is the non-volatile data storage area. These two memories map into the same address space on a bit for bit basis. Data is transferred from the RAM into the EEPROM by activating the STORE signal. Data is copied back into the RAM from the EEPROM by activating the RECALL signal. If data A is in EEPROM and data B is written to RAM, the data in the EEPROM is not changed until the STORE signal is activated. If the STORE signal is not activated, the data in EEPROM will not change. Upon activation of the RECALL signal, data A will again be presented in the RAM.

An NVRAM is typically small. NVRAMs currently in usage contain only 256 separately addressable locations. This addressing uses only 8 address bits. In a system with 24 addr...