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MINIMIZING POWER IN HIGH PERFORMANCE PLAs

IP.com Disclosure Number: IPCOM000037165D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 5 page(s) / 159K

Publishing Venue

IBM

Related People

Ditlow, GS: AUTHOR [+2]

Abstract

When designing high performance PLAs, minimizing power is a critical design issue. In this article, an algorithm is presented which personalizes the p-device pull-ups in the AND-array to significantly reduce DC power.

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MINIMIZING POWER IN HIGH PERFORMANCE PLAs

When designing high performance PLAs, minimizing power is a critical design issue. In this article, an algorithm is presented which personalizes the p- device pull-ups in the AND-array to significantly reduce DC power.

DEFINITIONS: DC Power is defined as the power dissipated after the signal has changed state and has settled to a steady state. This occurs typically in NMOS designs when there is an active path between power and ground. For an NMOS NOR circuit, if any of the pull-down devices are on, then DC power is dissipated.

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AC Power is the power dissipated when the circuit switches state from 0 T 1 or 1 T 0. For capacitance C and the voltage swing V, the AC power is computed by 0.5 x CV2 .

Figs. 1-3 illustrate a PLA and the Boolean equations when the PLA is implemented using NORs. The primary inputs are {x1, x2, x3}, the primary outputs are {y1, y2} and the product terms are {p1, p2}.

DYNAMIC PLAs: Consider a dynamic PLA which precharges in d1 and evaluates in d2 . During d1, the AND array is precharged to 0 while the OR-array is precharged to a 1 (see Figure 4). The only power dissipated during the precharge phase d1 is AC switching power since no active path exists between power and ground.

During the evaluate phase d2, if a product term pi is pulled down, then DC power is dissipated since there is an active path from power to ground. The circuit in this mode of operation looks like NMOS, which

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dissipates a large amount of DC power. One way of eliminating this power is to use CMOS. However, PLA's typically have a large number of pulldowns in a product term. The corresponding CMOS circuit requires a large number of p- devices in series. Unfortunately, this creates unacceptable up-level noise margins and slow output rise times.

CMOS COMPROMISE: A compromise between NMOS and CMOS is to place one more p-device in series with the d1 p-device. This is shown in Fig. 5 for product term p1 . For proper operation, the gate of this p-device must be a Boolean function which is a subset of the Boolean function trying to pull the product term low. That is, if the pull-down function for product term pi is fi ,then an acceptable function for the gate of the p-device is gi_fi.

In the example of Figs. 1-3, product term p1 = x -1 x3. When implemented in NORs, the pull-down function f1 =x1 +x -3. The function g1 for the gate of the new p-device must then be one of the following functions:

1

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1. {0} - NMOS with DC power when a pull-down is active;
2. {x1} - almost CMOS with DC power eliminated when x1 =1;
3. {x-3}- almost...