Browse Prior Art Database

Four-Way EVENT TRACE

IP.com Disclosure Number: IPCOM000037171D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 4 page(s) / 52K

Publishing Venue

IBM

Related People

Bello, KA: AUTHOR [+2]

Abstract

The Four-Way Event Trace mechanism creates a single integrated trace listing of events occurring in four independent microprocessors. This allows easy comparison of whether a given event on one microprocessor occurred earlier or later than an event on another microprocessor. This capability is essential when debugging problems involving the interaction of multiple microprocessors on a DASD control unit.

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Four-Way EVENT TRACE

The Four-Way Event Trace mechanism creates a single integrated trace listing of events occurring in four independent microprocessors. This allows easy comparison of whether a given event on one microprocessor occurred earlier or later than an event on another microprocessor. This capability is essential when debugging problems involving the interaction of multiple microprocessors on a DASD control unit.

This four-way event trace mechanism is composed of five elements (see Fig.
1):

1. One two-way event trace mechanism on each cluster. This mechanism merges the stream of trace entries from each of two local microprocessors into a single 8kx8 RAM storage array. The entries are written into the array in chronological order, and one bit in each entry identifies the processor that wrote the entry. The two-way event trace mechanism is a dual-port wraparound queue with a single pointer that is shared by the two microprocessors. When the queue becomes full, the oldest entries are overlayed, so that the buffer always contains the 8k most recent entries. This is illustrated in Fig. 2.

2. Two signals between the two event trace mechanisms. One signal indicates to the Cluster 1 event trace mechanism whenever SPO or SP1 makes a trace entry. The other signal indicates to the Cluster 0 event trace mechanism whenever SP2 or SP3 makes a trace entry.

3. Counter associated with two signals between the two event trace mechanisms. Each event trace mechanism contains a counter. This counter increments whenever the signal indicates that the other cluster stores a trace entry. Each trace entry that is stored into the array is formatted into two sections. The first section contains the entry itself, and indicates which microprocessor stored the entry. The second section is loaded with the counter's value at the time of the local trace entry. Thus, the counter, with information about the other cluster's trace operation, is "piggybacked" onto local trace entries, and is loaded into the array. At the same time, the counter is reset.

4. Simultaneous break point mechanism. This mechanism stops both event traces and all four microprocessors at precisely the same time.

5. Postprocessor program. This program examines the two trace listings and merges them together into a single listing. It begins after the break point mechanism has stopped all four microprocessors. It matches trace entries in one cluster's array with their associated piggyback entries on the other cluster. By matching these indicators, the postprocessing program is able to merge all the entries in correct chronological order.

Four Storage Path Event Trace Example: The following scenario describes a typical sequence of events during four-way event tracing.

1. Four-way event trace is initialized on both clusters.

1

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2. SP2 on CL1 creates a trace entry.

a. CL1 Event Trace stores the entry with

alternate cluster bits = 00.

b. CL1 indicates to CL0 that a trace entry has...