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Error Detection and Correction for Storage Members to Correct Long and Short Error Bursts

IP.com Disclosure Number: IPCOM000037173D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 77K

Publishing Venue

IBM

Related People

West, SC: AUTHOR

Abstract

Data are recorded onto a storage member with error correction and detection redundancies. The recording is interleaved in a manner that most errors result in one byte of error in each of the interleaved portions. Recording can be performed in one or more tracks while using the same error correcting interleave. Error detection redundancies are located within each data field to be error corrected. Error location pointers are provided. Error processing includes evaluating location and magnitude of each detected error. Error correction is pipelined.

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Error Detection and Correction for Storage Members to Correct Long and Short Error Bursts

Data are recorded onto a storage member with error correction and detection redundancies. The recording is interleaved in a manner that most errors result in one byte of error in each of the interleaved portions. Recording can be performed in one or more tracks while using the same error correcting interleave. Error detection redundancies are located within each data field to be error corrected. Error location pointers are provided. Error processing includes evaluating location and magnitude of each detected error. Error correction is pipelined.

Fig. 1 shows the base sector arrangement for interleaving the error correction code (ECC) 6 over five code blocks in the sector. Each code block has ECC redundancy for enabling detection and correction of a predetermined plurality of errors. Each block has a plurality of

(Image Omitted)

error correction codewords which share a plurality of error detection codewords (EDCs) for generating error pointing to locations of any errors. Fig. 2 shows the basic interleave sequence as described by the code block number and the EDC row within the code block.

The logical recording relationships of the tracks, ECC and EDC redundancies are described by the following equations: (1) B = (1 + (J-1) modulo 5) + 5 (F L*(J-1)/80)

(2) R = (16/M) (L-1) + C J/5 - (16/M * F L(J-1)/80

where -

B = block number

R = row number

C = ceiling function

F = floor function

M = number of recording tracks (1,2,4,8,16)

L = recording track number

J = EDC sequence number

The ECC generator polynomial is selected to be:

(3) G(X) = (X + T0) (X + T1) (X + T2)

(4) G(X) = X3 + T198X2 + T198X1 + T3

where the Galois field of 256 elements is defined by the

polynomial

(5) X8 + X4 + X3 + X2 + 1

where the coefficients of the polynomial are from the Galois

field of two elements.

T is a companion matrix of usual design, T0 is the identity m...