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PLL Stabilization and Noise Immunity With Manchester Differential Encoding

IP.com Disclosure Number: IPCOM000037175D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 75K

Publishing Venue

IBM

Related People

Garcia, C: AUTHOR [+3]

Abstract

Shown in Fig. 3 is a device that allows the synchronization of a Phase- Locked Loop PLL on Manchester differential encoded bits. It minimizes recovered clock jitter, when an incoming Manchester signal is dirtied with noise and phase jitter, or if a Manchester code violation has been introduced. Rectifying the Direction of the Manchester Transistion

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PLL Stabilization and Noise Immunity With Manchester Differential Encoding

Shown in Fig. 3 is a device that allows the synchronization of a Phase- Locked Loop PLL on Manchester differential encoded bits. It minimizes recovered clock jitter, when an incoming Manchester signal is dirtied with noise and phase jitter, or if a Manchester code violation has been introduced. Rectifying the Direction of the Manchester Transistion

The PLL phase comparator input needs a rising Manchester transi

(Image Omitted)

tion, whereas the Manchester transition of the incoming signal may be sometimes rising, sometimes falling. If the PLL input transition has the good direction, it will have the good direction also on the next bit if this next bit is a "zero", and it will have the bad direction if this next bit is a "one", as shown in Fig.
2.

As shown in Fig. 2, a 16-step-by-bit counter is started at each incomming transition. It can reach step 12 only during a "one". If the incoming signal is at an up level, it is inverted before entering the PLL; if it is at a down level at step 12, it is supplied to the PLL unchanged. Minimizing a Manchester Code Violation Impact

As shown in Fig. 3, if one Manchester transition is missing, the PLL output clock jitter is prohibitive.

When the counter reaches step 19, an artificial transition is generated at the PLL input to replace the missing one (theoretical position: step 16); moreover, during synchronization patterns, violation is allowed to be i...