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Wafer Burn-In Isolation Circuit

IP.com Disclosure Number: IPCOM000037197D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Adams, RD: AUTHOR [+2]

Abstract

To avoid loss of packaging cost of chips found to be faulty at the burn-in test level, chips are tested and burn-in stressed at the wafer level. Power, ground and a signal line are routed to each chip on the wafer via diffusions through kerf regions. The signal line is routed to each chip through a diode and fuse linkage. All circuits needed for dynamic testing are incorporated in each chip and are started by a signal on the signal line. A first test prior to stressing identifies bad chips which are then isolated from all other chips by fuse blowing. Thus, wafer level burn-in testing is performed and bad chips are identified and discarded before final packaging and module testing.

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Wafer Burn-In Isolation Circuit

To avoid loss of packaging cost of chips found to be faulty at the burn-in test level, chips are tested and burn-in stressed at the wafer level. Power, ground and a signal line are routed to each chip on the wafer via diffusions through kerf regions. The signal line is routed to each chip through a diode and fuse linkage. All circuits needed for dynamic testing are incorporated in each chip and are started by a signal on the signal line. A first test prior to stressing identifies bad chips which are then isolated from all other chips by fuse blowing. Thus, wafer level burn-in testing is performed and bad chips are identified and discarded before final packaging and module testing.

By having all interconnecting lines between chips go through diffusions in the kerf regions, there is no chance of ingress of corrosion possible through exposed metal after chips are diced.

The diode and fuse linkage in the signal line to each chip, as shown in the figure, prevents current from one chip flowing to a neighboring chip and permits total chip isolation by blowing fuses prior to burn-in stressing. In the event that there is a coincidence of a bad diode and a bad chip preventing testing all interconnected chips, segments of wafers, e.g., quadrants, are totally isolated and powered for testing individually. The figure shows a wafer quadrant 2, with all chips C (only two chips are shown) in the quadrant supplied by power to pad 4, a test start si...