Browse Prior Art Database

NA Generation for Fast Memory Access in a 386-Based System

IP.com Disclosure Number: IPCOM000037200D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Arroyo, RX: AUTHOR [+2]

Abstract

Disclosed is a method to attain high performance memory access speeds by clever utilization of the pipeline feature of the 80386SX CPU (running at 16 Mhz) such that external hardware is minimized. In addition to low cost as a design objective, a performance target of 0 wait states (with 100 ns memory) was set for CPU accesses to planar memory. In order to achieve this goal, the bus controller and memory controller utilized the full capability of the 80386SX address pipelining feature.

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NA Generation for Fast Memory Access in a 386-Based System

Disclosed is a method to attain high performance memory access speeds by clever utilization of the pipeline feature of the 80386SX CPU (running at 16 Mhz) such that external hardware is minimized. In addition to low cost as a design objective, a performance target of 0 wait states (with 100 ns memory) was set for CPU accesses to planar memory. In order to achieve this goal, the bus controller and memory controller utilized the full capability of the 80386SX address pipelining feature.

To achieve the performance objective of 0 wait states, the page-mode technique was used to access memory. This method of accessing memory is much faster than the normal mode because once the row address has been strobed, subsequent accesses to the same page only requires a CAS strobe. As a result of using this technique, however, bus cycles to memory vary due to whether or not a memory access is to the same page.

Since memory bus cycles can vary from 0 to 3 wait states, the bus controller, which is the primary interface to the CPU, could request pipelining immediately after detecting that a memory cycle is in progress. This would require the memory controller, however, to implement logic to latch the CPU memory address for long memory bus cycles.

To avoid latching the CPU addresses using external VTL logic, the NA signal is generated to the processor in such a way that the CPU acts as the latch for the addresses. Since the m...