Browse Prior Art Database

Bus Controller Synchronization

IP.com Disclosure Number: IPCOM000037202D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Arroyo, RX: AUTHOR [+2]

Abstract

Disclosed is a method to generate a synchronization signal to keep a primary bus controller, a secondary specialized memory bus controller, and a 80386SX CPU synchronized. This synchronization signal informs the memory controller of the beginning of a new bus cycle.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 3

Bus Controller Synchronization

Disclosed is a method to generate a synchronization signal to keep a primary bus controller, a secondary specialized memory bus controller, and a 80386SX CPU synchronized. This synchronization signal informs the memory controller of the beginning of a new bus cycle.

Fig. 1 shows a high level block diagram of the interface connection between the two bus controllers and the CPU. The ADS signal from the CPU allows it to indicate to the system when a bus cycle has begun. The Primary bus controller then controls address pipelining through the use of the NA signal, and it controls bus cycle termination through the use of the READY signal. The secondary memory controller monitors the CPU output control signals and the address lines waiting for a memory cycle but has no direct control of the CPU except through the primary bus controller. The memory controller indicates the end of a memory bus cycle though the use of the MEM RDY signal to the primary bus controller. The START signal from the primary bus controller is used by the secondary memory controller to qualify CPU output signals.

The 80386SX CPU indicates the beginning of a new bus cycle definition by driving the ADS signal low. If the CPU is pipelining, the ADS signal will become active for the next bus cycle before the current bus cycle is complete. In this case, the ADS signal will remain active until its associated bus cycle begins (i.e., when READY is returned for the current bus cycle). The control and address lines are guaranteed to be valid at the rising edge of ADS. Once the bus cycle has been initiated, the CPU drives ADS back high.

(Image Omitted)

Since the memory controller is not aware of whether pipelining is in effect, t...