Browse Prior Art Database

Automatic Detection/Implementation of Staggered Refresh

IP.com Disclosure Number: IPCOM000037204D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Arroyo, RX: AUTHOR [+3]

Abstract

Disclosed is a method which uses less system bus bandwidth for memory refresh by automatically detecting when a staggered refresh is required to minimize power supply current requirements. This method relates to a PS/2 computer containing sockets for Single In-line Memory Modules (SIMMs). Each SIMM may contain 1 megabyte, 2 megabytes, or 4 megabytes of dynamic RAM, which require periodic refresh cycles.

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Automatic Detection/Implementation of Staggered Refresh

Disclosed is a method which uses less system bus bandwidth for memory refresh by automatically detecting when a staggered refresh is required to minimize power supply current requirements. This method relates to a PS/2 computer containing sockets for Single In-line Memory Modules (SIMMs). Each SIMM may contain 1 megabyte, 2 megabytes, or 4 megabytes of dynamic RAM, which require periodic refresh cycles.

Functionally, the 1 megabyte SIMMs are composed of 1 bank of 256K x 4 bit memory modules. The 4 megabyte SIMMs are composed of 1 bank of 1024K x 4 bit memory modules. The 2 megabyte SIMMs, however, are composed of 2 banks of 256K x 4 bit memory modules.

During normal operation with 2-megabyte SIMMs, 1 bank is operational and the other bank is in standby mode. This results in a current requirement that is just slightly greater than the current requirements for a 1-megabyte SIMM. During a standard RAS-only refresh cycle, both banks would be refreshed simultaneously, requiring an additional 7-1/2 watts from the power supply just to perform refresh.

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One method to avoid this high power consumption is to implement staggered refresh, where one bank is refreshed first, followed by the second bank. However, in systems where 2-megabyte SIMMs are not installed, this adds an unnecessary delay to the refresh cycle.

In this system, the memory controller determines the type of SIMMs installed by decoding the...