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High-Speed Memory Test for Personal System/2 Power on Self Test

IP.com Disclosure Number: IPCOM000037212D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Massoudian, K: AUTHOR [+3]

Abstract

Disclosed is an enhanced memory testing algorithm for use in the Power- On Self-Test of the Personal System/2 (PS/2) computers. This new algorithm will reduce the memory test time by about 300%.

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High-Speed Memory Test for Personal System/2 Power on Self Test

Disclosed is an enhanced memory testing algorithm for use in the Power- On Self-Test of the Personal System/2 (PS/2) computers. This new algorithm will reduce the memory test time by about 300%.

The PS/2 systems have special code in their ROM modules (ROS) that perform the Power-On Self Test (POST). Part of POST is the memory test which first determines the size of memory present and then does an extensive read/write test to the memory. Due to the number of patterns tested, this memory test is the most time-consuming part of POST.

This invention has reduced the wait time for POST code approximately 300%, by speeding up the memory test. The storage test routine in POST was rewritten, employing a new algorithm that takes advantage of new instructions that have become available on the 80386 processor. The new algorithm, however, still performs the same in depth testing as the old one (i.e., the same patterns are used for testing and the same interface is used to communicate with other routines). The storage test algorithm uses five patterns that are written to the memory and read back and verified. The patterns used are the following:

Pattern # Pattern Written (in HEX)

1 AA55AA55

2 55AA55AA

3 01010101

4 5555AAAA

5 00000000 (except first

and last

word are FFFF)

The algorithm used is described below

/* ES and DS point to the memory block to be tested. */

/* CX contains double-word count of the block. */

F...