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Analog/Digital Converter Missing Code Test

IP.com Disclosure Number: IPCOM000037218D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Prilik, RJ: AUTHOR

Abstract

By using a digital/analog (D/A) converter as a stimulus and a random- access memory (RAM) to store passing test results as a RAM address, an A/D converter device is go-no-go tested without extensive data analysis. Measurement of response linearity is made without additional testing and minimal additional digital signal processing. Thus, a very large reduction in A/D device testing time and equipment is realized.

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Analog/Digital Converter Missing Code Test

By using a digital/analog (D/A) converter as a stimulus and a random- access memory (RAM) to store passing test results as a RAM address, an A/D converter device is go-no-go tested without extensive data analysis. Measurement of response linearity is made without additional testing and minimal additional digital signal processing. Thus, a very large reduction in A/D device testing time and equipment is realized.

Referring to the figure, A/D device under test (DUT) 28 receives analog input stimulus on line 36 from D/A 30. A/D 28 digital output feeds RAM 32 address in line 26. Both VLSI tester 34 and A/D 28 can be tri-stated. Lines 10 and 12 are conventional strobe and data inputs to D/A 30. Lines 14 and 16 are conventional strobe and tri-state inputs to A/D 28. The following are conventional RAM input/output (I/O) lines: address 18, read/write (R/W) 20, data out 22, data in 24, and clock 38.

To initialize RAM 32, tester 34 writes RAM 32 via lines 18, 20, 24, and 38 independent of D/A 30 or A/D 28 when A/D 28 is tri-stated via line 16. RAM 32 is written such that the data is the address. In a "run test" mode, each tester cycle strobes D/A 30 via strobe line 10, then A/D 28 is strobed via line 14. Missing codes do not write D/A data to RAM 32.

In a "read" cycle by tester 34, missing codes are found by reading RAM 32 via read/write line 20. Most significant bit data read via line 22 which is changed from that written in the "initialize" cycle indicates a missing code. Data stored in the low order bits in RAM 32 can then be analyzed for A/D linearity.

The width of data-in on line 24 to RAM 32 is a...