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Parallel Processing of Addresses for Fast Cache Access

IP.com Disclosure Number: IPCOM000037219D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Grove, MC: AUTHOR

Abstract

To improve computer cycle time, small adder circuits are used to permit the start of small random-access memory (RAM) files ahead of generation of a complete effective address in a large, slower adder circuit. Multiplexers and compare circuits are added to check that segment file addresses generated early by the small adders match the addresses generated later by the large adder circuit and to make corrections in the event of a mismatch.

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Parallel Processing of Addresses for Fast Cache Access

To improve computer cycle time, small adder circuits are used to permit the start of small random-access memory (RAM) files ahead of generation of a complete effective address in a large, slower adder circuit. Multiplexers and compare circuits are added to check that segment file addresses generated early by the small adders match the addresses generated later by the large adder circuit and to make corrections in the event of a mismatch.

Referring to the figure, operands 2 and 4 are, as usual, entered into adder 6 in their entirety to generate an effective address. Subsets of operands 2 and 4 are added in small adder circuits 8 and 10 which form addresses of small RAM segment file 12, translation-look- aside buffer RAM files 14 and 16, directory RAMs 18 and 20, and data caches 22 and 24. All of these small RAM files are addressed in parallel as soon as adders 8 and 10 provide the address data. Segment file 12 is addressed by data from adder 8 through multiplexer 25, while RAMs 14, 16, 18, 20, 22, and 24 are addressed directly by output from adder 10.

All of the RAMs are accessed in parallel and their outputs are sent to compare circuits 26, 28, 30, 32 and 34 as shown. A correct comparison (match) in compare circuits 28 and 30 results in selection of multiplexer 36 which then provides data to compare circuits 32 and 34 to select correct data from caches 22 and 24 via multiplexer 38.

The sum formed by adder 8 i...