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Vertical Capacitor VLSI Structure for High Voltage Applications

IP.com Disclosure Number: IPCOM000037233D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 5 page(s) / 131K

Publishing Venue

IBM

Related People

Nguyen, ST: AUTHOR [+2]

Abstract

A technique is described whereby a vertical capacitor structure is fabricated into very large-scale integrated (VLSI) circuitry, where space limitations are a prime consideration, for high voltage applications. This type of structure is particularly applicable where the low voltage limitations of a thin oxide dielectric capacitor precludes its use in higher voltage applications.

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Vertical Capacitor VLSI Structure for High Voltage Applications

A technique is described whereby a vertical capacitor structure is fabricated into very large-scale integrated (VLSI) circuitry, where space limitations are a prime consideration, for high voltage applications. This type of structure is particularly applicable where the low voltage limitations of a thin oxide dielectric capacitor precludes its use in higher voltage applications.

The concept describes a method of maximizing the capacitance per unit area. The vertical interdigitation of multiple conductive plates and dielectric layers achieves a three-fold increase in capacitance value per unit area, where a similarity exists in the dielectric constant and thickness.

Typically, thick oxide dielectric capacitors are required for applications above five volts and can be designed, as shown in Figs. 1a, 1b and 1c. The figures illustrate a vertical two-dimensional cross-section of a capacitor structure with a vertical slice made through the layers to expose an edge view of the structure. In Fig.

(Image Omitted)

1a, the dielectric capacitor consists of capacitor plates Metal 1 layer and dielectric layer formed by Metal-to-Metal 2 insulator. In Fig. 1b, the dielectric capacitor consists of Metal 1 layer and a polysilicon layer, with the dielectric layer formed by silicon glass. In Fig. 1c, the dielectric plates are the N-Well and the polysilicon layer, with the dielectric layer formed by the thick oxide. For each of these structures, as the capacitor values increase, the corresponding design area increases proportionally. As VLSI design requirements continue to require decreases in structural area, a new design approach becomes evident. As a result, the concept described herein provides a dielectric capacitor structure designed to maximize the dielectric capacitance values while minimizing the structural area requirements.

In Fig. 2, a vertical cross-sectional view illustrates the structure of an integrated combination of the three capacitors discussed in Fig. 1. The first pair of capacitor plates is formed, similar to Fig. 1a, by the Metal 1 and Metal 2 layers with the dielectric layer formed by the Metal-to-Metal 2 insulator. As in Fig. 1b, the second pair of capacitor plates is formed by the same Metal 1 layer and the polysilicon layer with the dielectric formed by silicon glass. As i...