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Array Coupled to LSSD Scan Mechanism: Scan Array

IP.com Disclosure Number: IPCOM000037239D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Marquart, DW: AUTHOR [+2]

Abstract

LSSD shift register latches (SRLs) may be used in a computer system for testing, diagnosis, debugging, and setting initial states. However, the shifting of information into and out of the scan path takes a good deal of time. To make it useful in the field for testing and diagnostics, and in the laboratory for debugging and testing, the function must be fast.

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Array Coupled to LSSD Scan Mechanism: Scan Array

LSSD shift register latches (SRLs) may be used in a computer system for testing, diagnosis, debugging, and setting initial states. However, the shifting of information into and out of the scan path takes a good deal of time. To make it useful in the field for testing and diagnostics, and in the laboratory for debugging and testing, the function must be fast.

The strings of SRLs (scan paths) that are to be scanned may be the recipient of data (scanning in), the source of data (scanning out), or both. A scan operation always moves information both into and out of a scan path. The mechanism that performs the scanning must provide data storage for the input information (unless a constant is to be scanned in, or the values being scanned out are to be scanned back in again) and for the output information (unless the output information is to be discarded).

Scanning is done under program control in a service processor. Scanning could theoretically be done by hardware alone, but analysis of results and control is too large for feasible hardware architectures. The difficulty in this is that if software is to control scanning, then scanning cannot be done to components required to run the software supervising the scanning.

A storage array to contain values to be shifted into a scan ring or to contain values shifted out of a scan ring.

Buffers, addressing mechanisms, and address registers with appropriate incrementers or decre...