Browse Prior Art Database

High Performance Risc Processor

IP.com Disclosure Number: IPCOM000037273D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 4 page(s) / 75K

Publishing Venue

IBM

Related People

Beakes, MP: AUTHOR

Abstract

A single-chip, programmable processor is disclosed that incorporates a two-stack architecture and hard-wired, single-cycle instructions to provide improved data access and processing performance.

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High Performance Risc Processor

A single-chip, programmable processor is disclosed that incorporates a two- stack architecture and hard-wired, single-cycle instructions to provide improved data access and processing performance.

The processor is a 16-bit programmable, reduced instruction set computer. Fig. 1 shows a block diagram of the processor, and Fig. 2 shows a typical system configuration using the processor. The two- stack architecture uses one stack for data manipulation and the other stack for storing the return addresses of subroutine calls. Both stacks share a common off-chip memory (256x16 RAM), but each has its top two elements located on chip. The processor can also directly address 8K 32-bit instructions and 8K 16-bit data.

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The processor was designed to execute the FORTH computer language directly in hardware. A flexible instruction set along with separate instruction, data, and stack ports make it possible to perform an instruction fetch, data access, stack operation, and an ALU operation in a single cycle. Multiply step and divide step instructions allow for signed and unsigned multiply and divide in 19 to 25 cycles.

The processor is packaged in a 144-pin grid array, has TTL compatible inputs and outputs, uses a 5-volt power supply, and operates at a 10-MHz cycle rate over the military temperature range. The processor is fully testable using level- sensitive scan design (LSSD) rules. To achieve the 10-MHz cycle rate, instruction fetches and data accesses are pipelined using external address and data registers.

Instructions consist of an 8-bit control field, 8-bit ALU field, and a 16-bit literal field. The literal field is used to call, jump, or data address or as immediate data. There are four types of instructions which are denoted by the two most significant bits of the control field. All instruction types allow for ALU operations to be specified in the ALU field. The four instruction types are defined as follows.

INSTRUCTION TYPE DESCRIPTION 00 PROGRAM CONTROLCONDITIONAL/UNCONDITIONAL CALL, JUMP, AND RETURN 01 EXTENDED ALU SIGNED/UNSIGNED MULTIPLY AND DIVIDE 10 DATA ACCESS READ/WRITE DATA MEMORY 11 INTERNAL ACCESS READ/WRITE INTERNAL REGISTERS

The control field formats for the four instruction types are as follows:

INSTRUCTION TYPE BITS DEFINITION

ROGRAM CONTROL 2 RETURN STACK ENABLE

3 +PUSH/-POP STACK

4-5 CALL, JUMP, RETURN SELECT

1

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00 NO CHANGE

01 CALL

10 RETURN

11 JUMP

6 CONDITIONAL/UNCONDITIONAL SELECT

0 UNCONDITIONAL

1 CONDITIONAL

(BASED UPON MSB OF TREG)

7 TREG INPUT SELECT

0 ALU OUTPUT

1 DATA INPUT BUS

EXTENDED ALU 2 DATA STACK ENABLE

3 +PUSH/-POP STACK

4-5 MULTIPLY/DIVIDE STEP SELECT

00 NORMAL ALU OPERATION

01 RESERVED

10 MULTIPLY STEP

11 DIVIDE STEP

6 DOUBLE SHIFT SELECT

7 TREG INPUT SELECT

DATA ACCESS 2 DATA STACK ENABLE

3 +PUSH/-POP STACK

4 +WRITE/-READ DATA

5-6 DATA ACCESS SELECT

00 ADDR=TREG WR-DATA-NREG

01 ADDR=NREG WR-DATA-TREG

10 ADDR=LREG WR-DATA-NREG

11 ADDR=LREG WR...