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A/D Auto-Zero Scheme

IP.com Disclosure Number: IPCOM000037308D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 5 page(s) / 135K

Publishing Venue

IBM

Related People

Buchholtz, TC: AUTHOR [+4]

Abstract

A circuit shown in Fig. 1 allows for the periodic cancellation of flash A/D converter DC offsets. These DC offsets come from A/D front-end amplifier offsets, comparator offsets, chip switching noise which causes an effective DC offset, AC noise synchronous with the A/D sampling clock, chip thermal gradients, etc. A variable offset preamplifier to the A/D accepts a five-bit digital signal to control its offset such that zero input to the A/D gives the zero output code. The digital five-bit offset code that gives closest to the A/D zero output code is stored and maintained between A/D zero operations. The logic for the zero operation in its simplest form counts through the possible five-bit offset codes until the A/D output produced the zero code.

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A/D Auto-Zero Scheme

A circuit shown in Fig. 1 allows for the periodic cancellation of flash A/D converter DC offsets. These DC offsets come from A/D front-end amplifier offsets, comparator offsets, chip switching noise which causes an effective DC offset, AC noise synchronous with the A/D sampling clock, chip thermal gradients, etc. A variable offset preamplifier to the A/D accepts a five-bit digital signal to control its offset such that zero input to the A/D gives the zero output code. The digital five-bit offset code that gives closest to the A/D zero output code is stored and maintained between A/D zero operations. The logic for the zero operation in its simplest form counts through the possible five-bit offset codes until the A/D output produced the zero code. In this case, the A/D has a signed input, and the A/D zero output code is chosen to correspond with one half of the full scale input voltage range. The A/D input is differential, so the input preamplifier converts the differential signal to single ended and centers its swing on a half of full scale reference voltage. On flash (parallel) A/D converters, this half of full scale reference point is the middle of the A/D resistor ladder.

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Fig. 1 shows the preamplifier circuit. It accepts a 0 to 1vp-p differential signal at connector pins GB0 and FD0, converts it to single-ended, and centers it on the flash A/D resistor ladder midpoint. The single ended output appears at connector pin G10. Another copy of the output appears at connector pin F20. The preamp also requires an external capacitor for the common mode control loop at connector pin G30. Connector pin BC0 also connects to connector G30 through an ESD protect resistor. Connector pin BM0 inputs the flash A/D resistor ladder midpoint voltage as a reference for the common mode control loop. Connector pin BH0 is a CMOS logic signal that HOLDS the common mode loop and disconnects (zeros) the input signal when it is high, and allows normal operation otherwise. Connector pin BP0 (PREF) is a p-channel current source reference voltage. Connector pin BN0(NREF) is an n-channel current source reference. Connector BA0 is an NPN current source reference voltage from an on-chip reference circuit. Connector GV0 is a 2.25-volt on-chip reference voltage. Connector BK0 is a .2 ma current from an on-chip reference.

The preamp input signal is AC coupled to inputs +/- A/D IN (GB0 and FD0). The input signal passes through transmission gate switch pairs made up of T1, T3 and T2, T4. These switches are opened when the preamp is in hold (zero) mode which prevents the AC coupling capacitors from changing their DC level as well as providing the zero input level to the preamplifier. In normal operation the input signal passes through the closed switches to resistors R1 and R2 where the input signal establishes a new DC reference point. The input reference voltage at node 4 is approximately 3.1 volts. P-channel device T23 keeps 1 ma...