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Browse Prior Art Database

Method to Compute the Random Photo Yield of Integrated Circuits

IP.com Disclosure Number: IPCOM000037312D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Guedj, D: AUTHOR [+2]

Abstract

The random photo yield represents in actual circuits a major portion of the yield detractors (>70% of faults for mature process) in chip manufacturing. It is therefore important to be able to compute accurately random yield of existing and future products.

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Method to Compute the Random Photo Yield of Integrated Circuits

The random photo yield represents in actual circuits a major portion of the yield detractors (>70% of faults for mature process) in chip manufacturing. It is therefore important to be able to compute accurately random yield of existing and future products.

A standard way to compute random photo yield is to throw random defects on the different levels of a layout and select the defects creating faults with shape- checking programs. Once the average number of faults per defect type is known, the yield becomes an unique function of the number of faults, defect density and defect size distribution.

All known programs have in common the dot-throwing method, as described in [1]. In order to give an accurate value of the average number of faults, the starting number of defects must be large. These programs take typically several hours of CPU time on large mainframes.

Future chips with more complex features, smaller groundrules, larger chip sizes, and more intricate failure modes will require, using this method, extremely large memory size and CPU time.

That is why we have developed this new method much which is faster and more accurate than the dot-throwing approach.

The present disclosure is based on the definition of critical area defined in [2], for instance.

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Considering a defect of size 2R, it will create a fault if it falls within the critical area. For two parallell lines, the critical area for short circuit is represented in Fig. 1 by the cross-hatched area.

There are simple geometrical relationships between the critical area and the starting layout shapes. This is the basis of our invention.

As an example, the critical area of more complex conductors is represented by the hatched area for opens (Fig. 2(a)) and shorts (Fig. 2 (b)). For a short circuit, we can compute the critical area by expanding the original shapes by R, intersecting the resultin...