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Transmission Delay Cancellation Mechanism on Very High Speed Bidirectional Buses

IP.com Disclosure Number: IPCOM000037313D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

Debord, P: AUTHOR [+2]

Abstract

On a high speed bus (around 30 ns cycle) where delay transmission on a medium is significant versus cycle time, the best way to ensure correct data latching at the receiving end is to send a sampling clock along with the data bus. However, this solution can be impractical in a multichip or multicard situation. Classical asynchronous techniques introduce extra heavy hardware and logic layers. The present disclosure offers a simple solution able to self-adapt to different hardware implementations. Consider Fig. 1, where one Central Switch Node (CSN) connects 1 to N satellites.

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Transmission Delay Cancellation Mechanism on Very High Speed Bidirectional Buses

On a high speed bus (around 30 ns cycle) where delay transmission on a medium is significant versus cycle time, the best way to ensure correct data latching at the receiving end is to send a sampling clock along with the data bus. However, this solution can be impractical in a multichip or multicard situation. Classical asynchronous techniques introduce extra heavy hardware and logic layers. The present disclosure offers a simple solution able to self-adapt to different hardware implementations. Consider Fig. 1, where one Central Switch Node (CSN) connects 1 to N satellites.

For transmission from the Central Switch Node (CSN) to the Satellite, data is sent with its own sampling clock (Master Clock=MsClk). Transmission delay is equal for clock and data and its impact is cancelled.

For transmission from Satellite to the CSN, a self-adjusted Virtual Xmit clock compensates for the data transmission delay so that data is delivered to the CSN with the proper phase shift versus the CSN sampling clock.

(Image Omitted)

A Reference Clock (RfClk) is delivered to each satellite and the CSN with no skew (delay paths equalled). The Master Clock (MsClk) coming from the CSN to Satellite N displays the same delay path as the Data Bus to this Satellite and drives the satellite. In each satellite a mechanism measures the delay Td between CSN and itself by comparing the RfClk and MsClk. Data to the CSN are released Td*Ns before the sampling time within the CSN.

The satellite Virtual Clock mechanism shown in Fig. 2 includes:

One RfClk to MsClk delay measure set. An oscillator operated at high frequency (example 5 ns cycle vs 30 ns Data Xmit rate) drives 2 counters one fed by RfClk and the other by MsClk. Phase shift or delay between RfClk and MsClk (Td) can be quan...