Browse Prior Art Database

Byte/Word Cycle Steal Mechanism

IP.com Disclosure Number: IPCOM000037317D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Davis, GT: AUTHOR [+5]

Abstract

This article describes a method and hardware implementation to transfer and detect a byte transfer over a word oriented cycle steal (CS) transfer device.

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Byte/Word Cycle Steal Mechanism

This article describes a method and hardware implementation to transfer and detect a byte transfer over a word oriented cycle steal (CS) transfer device.

In an application where a microprocessor controller is attached to an intelligent attachment card, and CS byte and word wide transfers from the controller to the attachment are to be supported, a method must be provided to distinguish a byte-wide from a word-wide transfer.

One way would be to have enough hardware to support both byte-and word- wide transfers. This increases the amount of hardware needed to perform controller/attachment interfacing.

Although a pure hardware approach may perform both forms of data transfers faster, there are some cases where the attachment card has a faster microprocessor, such as a digital signal processor. When this is the case, the CS data transfer mechanism on the attachment card does not have to be so fast.

Using a fixed single-word CS transfer mechanism together with some microcode assistance on the attachment card, a method has been developed to perform both byte-and word-wide CS data transfers. This method obviously requires less hardware than the pure hardware approach mentioned above.

The drawing illustrates the basic mechanism used in performing byte and word wide transfers through a word wide CS mechanism. In this case a microprocessor 1 is used as the microprocessor on the controller, and a microprocessor 2 as the processor on the attachment card. Microprocessor 1 issues a CS write of either a word or byte. The address is latched into the CS address register. The data (byte or word) is latched into a CS data register. These registers are used by the CS control logic to place the data in data RAM. At the same time the CS address which is 14 bits wide is placed in the CS indi...