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CMOS Exclusive-Or (Xor) Logic Circuit

IP.com Disclosure Number: IPCOM000037318D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Helwig, K: AUTHOR

Abstract

This article describes a CMOS XOR logic circuit in which AND or OR functions may be integrated in a space-saving manner.

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CMOS Exclusive-Or (Xor) Logic Circuit

This article describes a CMOS XOR logic circuit in which AND or OR functions may be integrated in a space-saving manner.

The XOR circuit (Fig. 1) consists of two complementary pairs of FETs T1, T2 and T3, T4, respectively. Logic signal A is applied to the gates of transistors T1, T2 and logic signal A to the gates of transistors T3, T4. Signals B and B are applied to both outer taps of the circuit, while the output signal X = A N B is emitted at the center tap.

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The frequently used function X = (A1$A2) N B is obtained by means of the standard logic block shown in Fig. 2. The logic block of Fig. 3 is formed by integrating the AND circuit in the XOR circuit of Fig. 1. The circuit of the AND$XOR (Fig. 3) is shown in Fig. 4. FETs T1 to T4 form the XOR circuit of Fig.
1. Signals A1 and A2 are ANDed by integrating additional FETs T5, T6, T7 and T8. Signal B is inverted by an inverter consisting of FETs T9, T10. Such integration saves the delay of at least one AND circuit. The performance and integration (layout) of the described circuit are extremely attractive. Similar advantages may be obtained by combining the XOR circuit with an OR circuit.

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