Browse Prior Art Database

Indirect Cache Access Mode

IP.com Disclosure Number: IPCOM000037319D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

A processor can request from the cache not only the result of a cache access but also the contents of the location pointed to by that access. This flexibility can be based on an architected or usage perceived requirement. Current System/370 processors that have cache memory are accessed with an address developed by the processor and return the contents, usually a double word, which includes the byte located at memory address requested. A new mode of cache access is described herein, an indirect cache access mode. When the cache is accessed in this mode, the contents of the address sent to the cache and the contents of the location addressed by one word, which contains the byte addressed by these contents, are both retrieved from the cache. The purposes and usefulness of the indirect mode are many and varied.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Indirect Cache Access Mode

A processor can request from the cache not only the result of a cache access but also the contents of the location pointed to by that access. This flexibility can be based on an architected or usage perceived requirement. Current System/370 processors that have cache memory are accessed with an address developed by the processor and return the contents, usually a double word, which includes the byte located at memory address requested. A new mode of cache access is described herein, an indirect cache access mode. When the cache is accessed in this mode, the contents of the address sent to the cache and the contents of the location addressed by one word, which contains the byte addressed by these contents, are both retrieved from the cache. The purposes and usefulness of the indirect mode are many and varied. These include but are not limited to: Responding to an architectural requirement.

Resolving a class of Address Generate Interlocks on

Data.

Resolving a class of Address Generate Interlocks on

Branch Targets.

For example, consider a processor with a multiple decode capability. While decoding two instructions, it perceives that the datum required to generate an address for the second instruction is requested by the first, for example by a LOAD instruction. Rather than await the normal response of the cache to the register loading, the processor invokes the indirect cache access mode on the original LOAD request. (Although it appears that such an approach is limited to those situations within S/370 where the displacement is zero, such a limitation is not intrinsic and can easily be circumvented by additional hardware.)

In response to an indirect mode access the cache will perform in the u...