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Indirect Targets in the Branch History Table

IP.com Disclosure Number: IPCOM000037321D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

By saving indirect target addresses in the Branch History Table (BHT), both the branch wrong guess (BWG) delay and the address generate interlock (AGI) delay can be avoided for changing target BCRs that are AGI'd.

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Indirect Targets in the Branch History Table

By saving indirect target addresses in the Branch History Table (BHT), both the branch wrong guess (BWG) delay and the address generate interlock (AGI) delay can be avoided for changing target BCRs that are AGI'd.

When a BHT incorrectly predicts the target of a BCR instruction whose target address is AGI'd by a previous instruction, the AGI and BWG delays are incurred in sequence. If the register modification that causes the AGI is a load or a load multiple, then both delays may be avoided by having a bit in the BHT that indicates that the target address (usually stored in the BHT) is not the actual address, but is an indirect address. That is, the address in the BHT is the address of a storage word containing the true target address. Since the BHT encounters the branch long before the branch is decoded there is time to make the two cache accesses that are required to obtain the target instruc- tion of the branch. This could be faster if the cache does the indirection.

When the target address of a taken branch is generated, it must be checked against the address of the target instruction that has already been fetched (and is about to be decoded or has just been decoded). If the branch is AGI'd, then there is time (while the AGI is resolved) to prepare to make the required update to the BHT in the case that the branch action is correct but the target address is wrong. Any error in target will be discovered as soon as th...