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Implementation of a Master Status Register Subsystem for I/O Channel Controller System Bus Interface Unit Transmit Function

IP.com Disclosure Number: IPCOM000037332D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Johnson, LE: AUTHOR

Abstract

The I/O Channel Controller (IOCC) System Bus Interface Unit (BIU) Master Status Register (MSR) is part of the BIU transmit section. The information stored in this register includes all the information necessary to run a cycle on the system bus: DMA or Load reply or INT; read or write; cycle count, etc.

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Implementation of a Master Status Register Subsystem for I/O Channel Controller System Bus Interface Unit Transmit Function

The I/O Channel Controller (IOCC) System Bus Interface Unit (BIU) Master Status Register (MSR) is part of the BIU transmit section. The information stored in this register includes all the information necessary to run a cycle on the system bus: DMA or Load reply or INT; read or write; cycle count, etc.

Fig. 1 shows the logic associated with the register, including an input multiplexer 1, the synchronization and arbitration logic for the three transmit requestors (DMA, LOAD, INT) 2, bus request generation logic 3, and the multiplexor feeding the system control byte 4.

The MSR simplifies the transmit controller by storing cycle control parameters, reducing the number of states in the controller implementation.

The MSR is also self-loading; higher performance is achieved by the register loading its own parms and requesting the system bus, overlapped with the start-up sequencing of the transmit controller. A detailed description of the MSR control follows. The MSR bit definitions are: Bit Function

0 read/write

1 reserved

2 string operation

3..7 dma word count or upper bits of load/store count

8 load reply cycle in progress

9 dma cycle in progress

10 interrupt cycle in progress

11 I/O error detected

Bits 8..10 control the loading of the register and subsequently the start of transmit controller cycles. The three inputs are requests for transmit c...