Browse Prior Art Database

Self-Aligned, Borderless Diffusion Contact Process for Ulsi

IP.com Disclosure Number: IPCOM000037336D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 4 page(s) / 86K

Publishing Venue

IBM

Related People

Breiten, C: AUTHOR [+5]

Abstract

Current process procedure requires that when making contact to the diffusion regions of the chip, a certain overlay tolerance be present to account for any level-to-level misalignment polygate to contact. This tolerance consumes a considerable amount of the circuit area and thus limits any improvements in chip density. Also, the use of separate photo levels to define the contacts and polygate features requires additional exposure systems, extensive processing and results in additional defect yield loss. This article describes a process technology which produces a self-aligned contact to the diffusion region that eliminates these problems and allows for increases in the circuit layout density. (Image Omitted)

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 4

Self-Aligned, Borderless Diffusion Contact Process for Ulsi

Current process procedure requires that when making contact to the diffusion regions of the chip, a certain overlay tolerance be present to account for any level-to-level misalignment polygate to contact. This tolerance consumes a considerable amount of the circuit area and thus limits any improvements in chip density. Also, the use of separate photo levels to define the contacts and polygate features requires additional exposure systems, extensive processing and results in additional defect yield loss. This article describes a process technology which produces a self-aligned contact to the diffusion region that eliminates these problems and allows for increases in the circuit layout density.

(Image Omitted)

The process follows typical CMOS procedure up to Gate Oxidation. Following Gate Oxidation, a photostep similar to buried contact photostep followed by an oxide selective etch is added to remove the gate oxide in the areas where contacts to the diffusion regions of the silicon substrate will be required. Next, a polysilicon deposition process is performed with 3000Ao of polysilicon, 140Ao of polysilicon oxide. This is followed by a phosphorous implant to lower the resistance of the subsequent polygate. 1000Ao of silicon nitride is then deposited to mask the polysilicon during the etch. The polygate photo-step must also be modified such that circular poly/nitride stacks are left in the area where the gate oxide has been removed. These areas will later be used for the self-aligned contacts to the diffusion regions. See Fig. 1.

Next TEOS spacers are added to the poly/nitride structures. The spacer etch also removes all gate oxide not protected by polysilicon. The N and P diffusion regions are then implanted around the gate electrode. However, since the poly/nitride structure over the diffusion area blocks the implant, one of the junctions has a circular, undoped region. See Fig. 2.

(Image Omitted)

The problem of this diffusion-open is solved by an anneal to diffuse the implant from the poly/nitride contact structure (doped...