Browse Prior Art Database

Compact Global Table for Management of Multiple Caches

IP.com Disclosure Number: IPCOM000037341D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Toney, EV: AUTHOR

Abstract

Multiprocessor systems typically have multiple cache storages sharing a common main store, and a system management facility for maintaining data integrity. This article describes an efficient scheme for such management especially useful where the number of processors with individual cache storages is more than a few.

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Compact Global Table for Management of Multiple Caches

Multiprocessor systems typically have multiple cache storages sharing a common main store, and a system management facility for maintaining data integrity. This article describes an efficient scheme for such management especially useful where the number of processors with individual cache storages is more than a few.

The scheme described in this article enables a shared memory system to recover the global state of a line of storage, a read-only copy of which had been given to one or more processors, to a known state of being absent from any cache. The scheme employs a table, the entries in which have a two-bit field recording the global state for each line of main storage and a sub-field which records in binary notation the number of processors, and thus caches, having a copy of the line of storage.

Fig. 1 illustrates a multiprocessor system in which the method can be useful. Each of a number of processors 10 in a multiprocessor system has a cache storage 12 which can be given a line of storage 14 from a system main storage 16 under the control of a main storage controller 18 by transmission through a switch 20. Under the control of 18 and located within or in association with 16, is a table 22 having an entry 24 which allows the system to keep track of the status of each line of storage 14 with respect to the various cache storages 12.

Fig. 2 illustrates the organization of a table entry 24. Two bits 26 characterize the global state of the corresponding line of storage 14, and a number of bits forming a sub-field 28 record the number of cache storages 12 to which the global state 26 relates. This recordation, instead of being one bit per cache storage 12, simply records the number of cache storages 12 in binary form.

Assuming that the processors for a shared memory system which includes P processsor-cache pairs are given IDs in a series from zero, the global state table uses an N+2 bit data field per line to maintain cache coherence data, wherein N equals the minimum number of binary bits to represent P. As shown in Fig. 2, two bits 26 of the table entry 28 serve a number of purposes depending on the global state. The following chart illustrates the usage: Global Description of
State Line's Status N-Bit Sub-Field Contents...