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Decrease the Time to Test RAM Array Logic by Using the ECC Design Logic to Find Errors

IP.com Disclosure Number: IPCOM000037355D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 59K

Publishing Venue

IBM

Related People

Bare, GT: AUTHOR [+3]

Abstract

This article describes a technique for use in a computer system to test the Error Correction Code (ECC) logic first and then perform a simple pattern test of the random-access memory (RAM) array.

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Decrease the Time to Test RAM Array Logic by Using the ECC Design Logic to Find Errors

This article describes a technique for use in a computer system to test the Error Correction Code (ECC) logic first and then perform a simple pattern test of the random-access memory (RAM) array.

Current engineering designs and increased RAM densities have caused a large increase in test time at power-up and in maintenance mode. In past designs of RAM tests the ECC was tested and then a large number of tests were done to test various patterns to induce noise and check many combinations of data versus address. The objective of this disclosed technique is to reduce all the RAM test patterns to test of all bits on and off and no cross picks. Then enable ECC and use the RAM for all other logic testing and let the ECC logic find the errors. If all RAM logic is designed with ECC, then by using the ECC design to detect errors, the testing time can be decreased substantially.

The ECC logic must be tested first and then a simple pattern test of the RAM array is all that is required. Adding ECC to the address parity bits has further decreased the time by eliminating time-consuming address tests. The RAM test sequence is described below. The ECC logic is tested first to verify that it does find errors and all check patterns are verified. The RAM test will run with ECC disabled due to testing of the check bit array and using data patterns. After the RAM array is tested, then ECC is enabled and the ECC logic is now the error checker.

RAM Array Test Sequence: This RAM test is re-entrant. Specify range on input. Bit pattern test and address test 0,5,A

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