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Modular Technique for Constructing Control Logic of a Pipelined Processor

IP.com Disclosure Number: IPCOM000037369D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue

IBM

Related People

Matick, RE: AUTHOR

Abstract

A technique is described whereby a set of modular building blocks and macros are interconnected by means of a uniform, standard interface to be used to design control logic of any pipelined processor. The blocks are designed so that they can be implemented in software as a modular timer, so as to provide an evaluation tool of relative instruction execution performance of any given pipeline.

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Modular Technique for Constructing Control Logic of a Pipelined Processor

A technique is described whereby a set of modular building blocks and macros are interconnected by means of a uniform, standard interface to be used to design control logic of any pipelined processor. The blocks are designed so that they can be implemented in software as a modular timer, so as to provide an evaluation tool of relative instruction execution performance of any given pipeline.

In prior art, methods for evaluating the performance of a processor equipped with a pipeline structure utilized evaluation timers. However, programs written for the evaluation were written such that interlocks between the various pipeline stages were required to be intricately interwoven. Changing the pipeline structure, or adding new features, were difficult and often required substantial reprogramming. Also, the programs required a high level of abstraction, with little resemblance to the actual hardware. As a result, the design of the timer and the actual design of the pipeline control structure became two separate problems.

The concept described herein provides a modular building block approach so as to overcome interwoven and reprogramming problems. The technique uses a "User Friendly Modular Timer" approach to allow a processor designer to easily make changes to the pipeline data flow structure and to run a set of instruction trace tapes through the timer so as to determine the relative number of...