Browse Prior Art Database

SSRB CPU - I/O Clock Control

IP.com Disclosure Number: IPCOM000037379D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 5 page(s) / 117K

Publishing Venue

IBM

Related People

Boston, JA: AUTHOR [+2]

Abstract

This article describes the implementation of programmable hardware to switch between two asynchronous clock rates and ensure clock control stability. This design has a programmable feature which allows from 0-4 cycles to be programmed to remove metastability. This permits a variable wait-time between the two clock rates in order to tune to the proper switching point.

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SSRB CPU - I/O Clock Control

This article describes the implementation of programmable hardware to switch between two asynchronous clock rates and ensure clock control stability. This design has a programmable feature which allows from 0-4 cycles to be programmed to remove metastability. This permits a variable wait-time between the two clock rates in order to tune to the proper switching point.

The implementation of this hardware is based on a previous metastability analysis performed on CMOS technology. The results recommended using double clocked latches in series to decrease the MTBF (Mean Time Between Failure) due to metastability. This article shows how a programmable feature was adapted to this recommendation to allow from 0 to 4 latches to be placed in series for metastability removal. This allows for maximum flexibility when debugging on the raised floor and provides tuning for optimum machine performance.

This hardware design can be used on two STIO chips (Storage-I/O Interface) of the ICP (Integrated Channel Processor) card. A logic function within the STIO called the SSRB (Synchronizing Storage Request Buffers) uses the metastability removal design in four different instances to switch clock control between the CPU rate and the integrated I/O rate so that data can be used at either clock rate.

(Image Omitted)

Metastability is an unstable condition that occurs when an input signal to a latch is changing at the time the latch clock is changing. The result is that the output of the latch may be at an undefined logic level. Metastability arises in the SSRB interface because of the use of two clocks that are asynchronous to each other, the CPU rate clock and the integrated I/O clock.

Fig. 1 shows the high level diagram of the metastability control logic in which there are five major functions: a programmable gate selector, a set/reset function at the I/O rate, MRL (metastability removal logic) at the CPU rate, a set/reset function at the CPU rate, and MRL at the I/O clock rate.

The sequence of operation is described below. Initially, clock control defaults to one of the two states, either I/O or CPU. For illustrative purposes, assume I/O initially has control of data.

When I/O execution has completed, the following sequence of events occur:

(Image Omitted)

A one shot pulse sets the I/O rate S/R latch.

The active output of the I/O rate latch is sent to the

MRL at the CPU Rate.

This CPU MRL then uses the programmable gate inputs to

wait x cycles

(0-4) before sending a one shot pulse to the I/O rate

1

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latch.

The one shot pulse sets the CPU latch and clock control

has now been transferred to the CPU rate.

When the CPU execution has completed, the control returns to the I/O rate with the following sequence of events: A one shot pulse resets the CPU rate latch.

The falling edge output of the CPU rate latch is sent to

the MRL at the I/O rate.

This I/O MRL then uses the programmable gate inputs to

wait y cycles

(0-4) be...