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5-Volt Signal Level Shifter in a 3-Volt Cmos Circuit

IP.com Disclosure Number: IPCOM000037380D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Busch, RE: AUTHOR [+3]

Abstract

A means is shown for interfacing 3-volt on-chip signal levels directly to 5-volt signal levels while avoiding stress conditions and possible DC current paths.

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5-Volt Signal Level Shifter in a 3-Volt Cmos Circuit

A means is shown for interfacing 3-volt on-chip signal levels directly to 5-volt signal levels while avoiding stress conditions and possible DC current paths.

Power supply standards become a problem as process technologies evolve and allow for greater circuit densities, speed, and lower power supply voltages. On-chip regulation provides a means for allowing internal circuits to operate at 3 volts, while the external power supply remains at 5 volts. In this way, transistors operate at a reduced voltage of 3 volts for which the process has been optimized, and avoid the undesirable stresses a 5-volt supply will exert if applied directly. A method is shown for interfacing from 3-volt signal levels directly to 5 volt signal levels while avoiding stress conditions and possible DC current paths.

Fig. 1 shows a 3-volt supplied inverter driving a 5-volt supplied inverter. This interface has several disadvantages, namely, transistors TP2 and TN2 both have their gate oxides exposed to 5-volt stress which is not acceptable if the device technology is optimized for 3 volts. Also, TP2 cannot be turned "off" completely because node A can only reach a 3-volt level through TP1 which causes DC to flow through TP2 and TN2 when node A is at 3 volts.

Fig. 2 shows the new circuit which solves both of the problems mentioned. As input "IN" rises, node NI1 falls, pulling node A low through diode TN2 and transistor TN4. With node A low, TP3 is turned on, pulling output "OUT" high to a full 5-volt level. Likewise, TP1 is turned on, node B is pulled to 5 volts, and TP2 is turned fully "off". By cross-coupling transistors TP1 and TP2, nodes A and B are alway...