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Bypass Latch Control of Long Shift Register Strings

IP.com Disclosure Number: IPCOM000037387D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 5 page(s) / 89K

Publishing Venue

IBM

Related People

McAnney, WH: AUTHOR

Abstract

Two methods are shown for reducing the time required to shift data into or out of portions of long serial paths in level-sensitive scan design (LSSD) structures. The structure consists of large numbers of shift register latches (SRLs) on each of n logic chips mounted on a wiring substrate or module. The scan-out port of one chip drives the scan-in port of the next, and all SRLs are chained together into one long shift register string. With this structure, some additional control over the string is desirable to reduce the time required to shift data to or from an individual chip or groups of chips. This control can be obtained with a bypass SRL that provides, on demand, a single-bit serial connection through a chip. Test access time to a single chip is reduced by planing the other n-l chips in bypass mode.

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Bypass Latch Control of Long Shift Register Strings

Two methods are shown for reducing the time required to shift data into or out of portions of long serial paths in level-sensitive scan design (LSSD) structures. The structure consists of large numbers of shift register latches (SRLs) on each of n logic chips mounted on a wiring substrate or module. The scan-out port of one chip drives the scan-in port of the next, and all SRLs are chained together into one long shift register string. With this structure, some additional control over the string is desirable to reduce the time required to shift data to or from an individual chip or groups of chips. This control can be obtained with a bypass SRL that provides, on demand, a single-bit serial connection through a chip. Test access time to a single chip is reduced by planing the other n-l chips in bypass mode.

Fig. 1 is a symbolic representation of the scan string through one chip. The scan-in port is driven by the scan-out of the previous chip

(Image Omitted)

(or by the tester for the first chip). The scan-out port drives the following chip (or the tester in the case of the last chip). Scanning is controlled by the Shift A and Shift B clocks that drive all chips in common. (When both Shift A and Shift B are "on", a flush mode is established in which the L1 and L2 latches of the SRLs follow the value on the scan data input.) In what follows it is assumed that there is no inversion in the serial path through the scan string.

The First Method: A scan string bypass is provided by adding a Stable Shift Register Latch (SSRL)[*] at the end of the scan string on each chip. Fig. 2 shows an SRRL consisting of an SRL plus a single stable L3 latch whose outputs do not change during a shifting operation.

The complete bypass structure is shown in Fig. 3. Its operations is as follows:

1. Turn power on.

2. Set the scan-in of the first chip to 1. Turn on both the Shift A and Shift B clocks. Set Bypass Select = 1. Now consider the scan string of the first chip. Since both A and B clocks are on, all SRLs of the string follow their scan data inputs. Ultimately the scan-out of the scan string becomes 1 (since there is no inversion

(Image Omitted)

down the string). Now both the D and the I inputs of the L1 latch of the SSRL are 1. Regardless of the initial state of the L3 latch, a 1 is loaded into the L1 and then into the L2 latch (and onto the scan-out of the chip) and the L3 latch. With 1 on the scan-out of the first chip (and, hence, the scan-in of the second chip) the same procedure occurs on the second string and on subsequent strings until the L3 latches on every chip are set to 1.

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3. Turn off the Shift A and Shift B clocks. Set Bypass Select = 0 to hold +L3 = 1 and -L3 = 0 on every chip. This is bypass mode. In this mode, the Shift A clock is gated through to the C input of the SSRL. A one-bit serial path is established through each chip, from scan-in port through the L1 and L2 of the...