Browse Prior Art Database

Electronic Architecture for a High Speed Bi-Directional Printer

IP.com Disclosure Number: IPCOM000037431D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Damon, BW: AUTHOR [+5]

Abstract

Disclosed is an electronic architecture for a bi-directional printer capable of high burst speed and high throughput. The architecture allows for optimized control of 3 major tasks: input and formatting of host data, real time control of the motors, and output of data to the print head.

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Electronic Architecture for a High Speed Bi-Directional Printer

Disclosed is an electronic architecture for a bi-directional printer capable of high burst speed and high throughput. The architecture allows for optimized control of 3 major tasks: input and formatting of host data, real time control of the motors, and output of data to the print head.

The architecture employs a single microprocessor and additional circuitry to control the mechanisms of the printer. The circuitry surrounding the microprocessor is architected to allow the two types of micro-code execution suspension; one is hardware interrupts and the other Direct Memory Access (DMA). The hardware interrupts are for tasks requiring real time control: data input from the host and notification of transport motor movement. The DMA requests are generated for tasks requiring only the transfer of data such as updating the print head wire fire information or updating the index motor phase lines.

The use of DMA for transfer of wire fire information to the print head gives the largest reduction in microprocessor overhead. Wire fire data is stored in a bit image format in RAM. Therefore, once the wire fire data has been formatted the microprocessor initiates the DMA transfers and is free to continue with other processing tasks.

DMA control of the index motor phase lines eliminates a high priority interrupt needed for precise index step control. By eliminating a high priority interrupt the processor can easily...