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Cache Design which Eliminates Cache Store Miss Penalty

IP.com Disclosure Number: IPCOM000037509D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Chuang, CM: AUTHOR [+2]

Abstract

A method and means for substantially eliminating the cache store miss reload penalty are provided. A set of store miss buffers which can store the address and data fields of information to be stored but are not in cache, which can send stored information to main memory, and which can recognize a subsequent load after a store to the same line are the provided means for eliminating the cache store miss reload penalty. The provided method utilizes the store miss buffer means to hold information which is the subject of a store miss and to prevent a full reload where the store miss is not followed by a load to the same line within a short time interval.

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Cache Design which Eliminates Cache Store Miss Penalty

A method and means for substantially eliminating the cache store miss reload penalty are provided. A set of store miss buffers which can store the address and data fields of information to be stored but are not in cache, which can send stored information to main memory, and which can recognize a subsequent load after a store to the same line are the provided means for eliminating the cache store miss reload penalty. The provided method utilizes the store miss buffer means to hold information which is the subject of a store miss and to prevent a full reload where the store miss is not followed by a load to the same line within a short time interval.

It is well appreciated that processors lose efficiency when they suffer cache misses. A good percentage of cache misses are cache store misses, where the word to be stored into is not located in cache. Previously, in such cases, the entire line including the word to be stored into would be read into cache, thus incurring a "penalty" due to the fact that the processor is required to conduct such a transaction and wait until the word is resident in cache prior to storing the word. While this penalty is reasonable if words in the line are to be read by (loaded into) the microprocessor shortly thereafter, the penalty is undesirable if the line is not shortly thereafter loaded into the microprocessor. Thus, it is desirable to avoid this penalty in such cases.

In order t...