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Parity Generation without Increasing Machine Cycle Time

IP.com Disclosure Number: IPCOM000037525D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Rosenthal, RR: AUTHOR

Abstract

The logic circuit described checks for parity errors in registers that could arise during a single machine cycle or during a longer period for which a register inhibit is active without adding delay time. This method is especially useful for combinational logic, where parity propagation is impractical and parity generation is often added just before logic output feeds into registers, thus increasing machine cycle time.

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Parity Generation without Increasing Machine Cycle Time

The logic circuit described checks for parity errors in registers that could arise during a single machine cycle or during a longer period for which a register inhibit is active without adding delay time. This method is especially useful for combinational logic, where parity propagation is impractical and parity generation is often added just before logic output feeds into registers, thus increasing machine cycle time.

Referring to the figure, a 32 bit register is comprised of master M2 and slave S2. An inhibit line I is attached to slave S2. Four parity bits are generated by an exclusive OR tree XOR corresponding to data held in slave S2. The four parity bits generated in XOR are latched in slave S4 concurrent with latching new data in slave S2. Note that output from slave S2 is sent to a data path DP as well as to parity generator XOR. Master registers all use the same system clock pulse and all slaves are clocked by a second, non-overlapping clock pulse. All latches pass data through when their clocks are active and latch up on the trailing edge of their respective clock pulses. Compare circuit C cascaded with the XOR tree forms a parity detection function for S4 and S2. A one bit register comprised of master M6 and slave S6 latches the parity detection results and feeds into error reporting logic ERL. Thus, parity is checked for slave S2 in every machine cycle. Parity is regenerated only when the data is...