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Fast Write Scheme for Memory Test Patterns

IP.com Disclosure Number: IPCOM000037531D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Lipa, RA: AUTHOR [+3]

Abstract

A fast write method is shown for loading various test patterns into a memory chip or imbedded memory array for functional test purposes.

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Fast Write Scheme for Memory Test Patterns

A fast write method is shown for loading various test patterns into a memory chip or imbedded memory array for functional test purposes.

Typical memory chips or imbedded memory arrays require multiple operating cycles for writing data patterns and initializing the array prior to performing a functional test. Writing test patterns and reinitializing when test patterns are changed can consume a large amount of test time. Further, for imbedded arrays it may be difficult to access specific physical locations necessary to properly test the array.

The figure shows one of eight word block decoders, typical for large segmented arrays, which activates secondary decoders (not shown) within a selected block. The same architecture is utilized for the bit block decoders (not shown). The word block decoder shown may also represent the primary word decoder in a small imbedded array.

Global timing signal WDR sets/resets latch L1 (T6, T7, T8, T9 & T10) and activates T1 to provide normal block decoding (NOR circuit T2, T3, T4 & T5). WDR also controls block precharge, secondary decoder selection and localized T/C generator activation as indicated. By adding device TX to the NOR decode circuit and controlling it with a common negative TEST pulse, all array blocks are activated simultaneously during a blanket write for any desired pattern. Normal operation is achieved by applying a positive TEST level to TX.

Because this fast write method co...