The Prior Art Database and Publishing service will be updated on Sunday, February 25th, from 1-3pm ET. You may experience brief service interruptions during that time.
Browse Prior Art Database

Reduced Polysilicon Wiring Capacitance

IP.com Disclosure Number: IPCOM000037532D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 1 page(s) / 11K

Publishing Venue


Related People

El-Kareh, B: AUTHOR [+2]


A method to reduce the polysilicon wiring capacitance in CMOS structuresis described.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 1

Reduced Polysilicon Wiring Capacitance

A method to reduce the polysilicon wiring capacitance in CMOS structuresis described.

The method shown reduces wiring capacitance while maintaining the polysilicon line conductivity. Referring to the figure, by utilizing existing blocking masks to block a boron, arsenic or phosphorus implant, the polysilicon can be left intrinsic (non-conductive) over defined regions other than the gate area. This technique solves three problems: 1) The parasitic capacitance between the intrinsic polysilicon and single crystal silicon (substrate) as well as the intrinsic polysilicon and adjacent intrinsic polysilicon is greatly reduced. A reduction of approximately 5X is estimated for the fringe capacitance and about a 1.3X reduction in area. This does not affect the metal to intrinsic polysilicon capacitance when the intrinsic polysilicon is covered with metal. 2) The effective thickness of polysilicon over thick oxide regions is greatly increased, thus, increasing the parasitic threshold voltage in those regions. 3) The suspected problems related with outdiffusion of species of one polarity into regions of the opposite polarity, through the silicide, are eliminated.

(Image Omitted)

Disclosed anonymously.