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Dual Polyimide Lift-Off Stencil for Thin/Thick Film Metallurgy

IP.com Disclosure Number: IPCOM000037609D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Fitzsimmons, JA: AUTHOR [+3]

Abstract

This article concerns a process improvement yielding a 10.5 um rack-free lift-off stencil film for substrate applications.

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This is the abbreviated version, containing approximately 100% of the total text.

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Dual Polyimide Lift-Off Stencil for Thin/Thick Film Metallurgy

This article concerns a process improvement yielding a 10.5 um rack-free lift- off stencil film for substrate applications.

Lift-off stencils for the generation of thin-film wiring on top of a substrate must meet stringent thickness requirements while being able to survive subsequent processing steps, in particular silylation, without cracking. Cracking propensity is minimized by preheating the cathode prior to etching, but their presence produces shorts in the top surface metallurgy.

The disclosed process improvement involves the production of an underlayer film composed of: (1) a lift-off polyimide (eg., Ciba-Geigy XU 284) baked to a required temperature, and (2) an insulating polyimide overcoat (eg., duPont RC 5878) baked to 230oC. (process restricted).

On top of the underlayer film, a silylated resist RIE barrier is built, as shown in the accompanying cross-section of the dual polyimide process after RIE. No post RIE lift-off stencil cracks occur in the finished stencil with or without cathode preheating.

In the Figure, the silylated resist 1 overlays the insulating polyimide 2 and the lift-off polyimide 3. The substrate 4, containing via 5, may be silicon, alumina, or glass ceramic.

Disclosed anonymously.

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