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Nitride Liner On PtSi for Prevention of Quartz Penetration

IP.com Disclosure Number: IPCOM000037612D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Kuhlman, DD: AUTHOR

Abstract

Disclosed is the use of a nitride liner in those semiconductor processes using lift-off stud and sputtered quartz combinations. The method results in enhanced Schottky barrier diode (SBD) electrical characteristics.

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Nitride Liner On PtSi for Prevention of Quartz Penetration

Disclosed is the use of a nitride liner in those semiconductor processes using lift-off stud and sputtered quartz combinations. The method results in enhanced Schottky barrier diode (SBD) electrical characteristics.

In the S stud insulator process (Fig. 1) the design permits the stud 1 to partially cover the PtSi contacts 2. The Schottky barrier diode (SBD) structure includes thermal oxide 3 and thermal nitride 4 layers. In order to minimize or prevent void formations between adjacent studs, a highly resputtered quartz 5 is deposited. This resputtered quartz has shown to penetrate the PtSi 6 where exposed. The quartz penetration causes poor Schottky characteristics, such as high leakage and poor ideality.

The disclosed method (Fig. 2) provides the deposition of a plasma-enhanced chemical vapor deposition (PECVD) nitride liner 7 immediately following the S stud liftoff step and prior to quartz 5 deposition. The nitride protects the PtSi 6 from any quartz penetration.

Disclosed anonymously.

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