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Dynamic Memory Interface Synchronization

IP.com Disclosure Number: IPCOM000037638D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Clark, SD: AUTHOR

Abstract

In a Motorola 68000 based system, several devices may be attached to the Motorola 68000 bus. One of these devices is generally a memory controller which interfaces the Motorola 68000 bus to a memory array. Other devices on this bus may also have the ability to do accesses to this memory controller, some of which may run off system clocks which are asynchronous to the system clocks of the memory controller. Since memory is usually a valuable commodity in a microprocessor based system, reducing any added delay to memory accesses will directly increase the performance of the system. A method may be used to dynamically synchronize the control signals in such a way as to minimize the added delay to the memory access by only synchronizing those control signals originating from devices running with separate system clocks.

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Dynamic Memory Interface Synchronization

In a Motorola 68000 based system, several devices may be attached to the Motorola 68000 bus. One of these devices is generally a memory controller which interfaces the Motorola 68000 bus to a memory array. Other devices on this bus may also have the ability to do accesses to this memory controller, some of which may run off system clocks which are asynchronous to the system clocks of the memory controller. Since memory is usually a valuable commodity in a microprocessor based system, reducing any added delay to memory accesses will directly increase the performance of the system. A method may be used to dynamically synchronize the control signals in such a way as to minimize the added delay to the memory access by only synchronizing those control signals originating from devices running with separate system clocks.

A signal can be generated and input to the memory controller such that the controller can determine that the current bus cycle is mastered by a device which is running asynchronously to the memory controller. In this case, synchronization of the necessary control signals will take place. For the case in which the device accessing the memory controller is running with clocks synchronous to the memory controller, the control signals may be passed directly into the control logic. The generic structure of this synchronization is shown in Fig. 1.

In a simplified system in which the memory controller is running with s...