Browse Prior Art Database

Extendable BICMOS Latch

IP.com Disclosure Number: IPCOM000037639D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Buchholtz, TC: AUTHOR [+3]

Abstract

This disclosure describes a high-density, high-performance extendable BiCMOS Polarity Hold L1 Latch. The Or-And-Invert function is realized by dotting the emitters of the data ports. The switching NFET is used to pull down the emitter follower circuit, eliminating the DC power required with the traditional resistor pull-down.

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Extendable BICMOS Latch

This disclosure describes a high-density, high-performance extendable BiCMOS Polarity Hold L1 Latch. The Or-And-Invert function is realized by dotting the emitters of the data ports. The switching NFET is used to pull down the emitter follower circuit, eliminating the DC power required with the traditional resistor pull-down.

Figure 1 shows a BiCMOS 2xN OAI L1 latch circuit. The latch is constructed with one 2xN OAI and two CMOS inverters in series, plus an additional BiCMOS output using part of the latch as a phase splitter. This reduces the device requirements and improves performance. The BiCMOS output provides high fanout and load insensitivity. The OAI gate is connected to the first inverter through pass-gate transistor N2.

When N2 is turned on by clock C0, it allows the BiCMOS OAI to overdrive the small inverter that makes up the first stage in the latch. Clock C0 also switches pull-down transistor N1 off the BiCMOS OAI, eliminating DC power in standby mode. The second inverter output is fed back to the input of the first inverter to form a basic latch.

Disclosed anonymously.

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