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Edge-Sealing Cap for a Surface Mount Array

IP.com Disclosure Number: IPCOM000037668D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Cerny, MT: AUTHOR [+4]

Abstract

Currently a seal between a substrate and a cap is provided by a backseal poured on the substrate with approximately .040 inch of backseal. This seal has been tested and proved reliable for first level non-thermal module packaging.

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Edge-Sealing Cap for a Surface Mount Array

Currently a seal between a substrate and a cap is provided by a backseal poured on the substrate with approximately .040 inch of backseal. This seal has been tested and proved reliable for first level non-thermal module packaging.

Modules with "C" pins require a maximum of .010 inch thickness of backseal. This .010 inch along the edge of the cap does not require a seal between the substrate and the cap.

Surface mount array modules with .010 inch thickness seals failed leak testing after thermal cycling. Failure was due to the fact that there was not a seal between the substrate and cap completely around the cap.

The present technique still uses the standard cap to form a moat so that when the substrate is placed in the cap, there is approximately .015 inch of space between the substrate and the cap, guaranteeing a fill of backseal in that space, which prevents any leaks.

The height of the cap also has been reduced approximately .013 inch, so that there is .010 inch - .015 between the top of the substrate and the top of the cap. This lower height provides extra clearance for any rework tool, while still providing a reliable seal.

Disclosed anonymously.

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