Browse Prior Art Database

Tungsten Alignment Marks for Electron Beam Lithography

IP.com Disclosure Number: IPCOM000037779D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-30
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Pearson, DJ: AUTHOR [+2]

Abstract

Disclosed is a technique by which electron beam alignment marks are fabricated in planar integrated circuit structures. These alignment marks (Fig. 1) allow registration of electron beam defined patterns on planar dielectric and low-Z metal films without the need to selectively remove these films over the alignment mark area.

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Tungsten Alignment Marks for Electron Beam Lithography

Disclosed is a technique by which electron beam alignment marks are fabricated in planar integrated circuit structures. These alignment marks (Fig. 1) allow registration of electron beam defined patterns on planar dielectric and low- Z metal films without the need to selectively remove these films over the alignment mark area.

Typical electron beam alignment systems rely on detection of back-scattered electrons from the edge of an alignment mark previously fabricated in the structure. Alignment mark edges covered with planarized dielectrics or metals (a common occurence in current on-chip wiring processes) exhibit insufficient contrast in the back-scattered signal for accurate alignment. The use of tungsten filled alignment marks results in enhanced contrast due to its large back- scattering coefficient and an alignment mark structure which is compatible with further planar processing.

These marks are easily fabricated at any stage in the process by etching alignment mark patterns in a planarized dielectric, depositing an appropriate adhesion layer and filling the alignment mark patterns with CVD tungsten. Subsequent etch-back of the tungsten results in the planarized alignment mark structure shown in Fig. 1. In the event that W studs are used to connect one wiring level to the next, alignment marks can be fabricated at all stud levels with no additional processing.

Disclosed anonymously.

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