Browse Prior Art Database

I/O Channel Controller (IOCC) System Bus Interface Unit (BIU) Transmit Controller

IP.com Disclosure Number: IPCOM000037783D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-30
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Johnson, LE: AUTHOR

Abstract

Disclosed is a finite state machine and gray-code counter implementation that provides system interface handshaking and data-flow control signals to accomplish DMA, Programmed Input/Output (PIO) load, and interrupt vector transactions with the system bus.

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I/O Channel Controller (IOCC) System Bus Interface Unit (BIU) Transmit Controller

Disclosed is a finite state machine and gray-code counter implementation that provides system interface handshaking and data-flow control signals to accomplish DMA, Programmed Input/Output (PIO) load, and interrupt vector transactions with the system bus.

The transmit controller is part of the IOCC BIU, which also includes a receive subsystem, and an interrupt subsystem.

The implementation described here has the advantage that requests for the system bus are made by a companion subsystem, while this controller loads a cycle counter and buffer pointers in parallel, decreasing complexity and increasing performance. Use of the cycle counter eliminates the need for different states to run PIO data, DMA data, and interrupt vector cycles, reducing the number of states.

During the initialization sequence, the cycle counter (labeled Gray Down Counter in Fig. 1) is loaded with the correct value depending on the type of transaction. This value is provided by another subsystem. When the counter indicates zero, the cycle is terminated. An overflow indication is provided to allow control beyond system data bus latch boundaries. 'Gray' coding is used so that other controllers on asynchronous clocks can read glitch-free samples of the counter's state.

Disclosed anonymously.

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