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Input Limiter Circuit

IP.com Disclosure Number: IPCOM000037793D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-30
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Davis, A: AUTHOR

Abstract

By means of a complementary metal oxide silicon (CMOS) circuit, voltage is controlled on an n-channel transistor which is used as a pass device and voltage limiter. The circuit provides full high voltage supply Vdd switching levels for CMOS input levels and requires no clocked inputs, while protecting against inputs higher than Vdd.

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Input Limiter Circuit

By means of a complementary metal oxide silicon (CMOS) circuit, voltage is controlled on an n-channel transistor which is used as a pass device and voltage limiter. The circuit provides full high voltage supply Vdd switching levels for CMOS input levels and requires no clocked inputs, while protecting against inputs higher than Vdd.

Referring to the figure, P channel device P1 is controlled by the input voltage and keeps the gate of device N1 at high supply voltage VDD as long as the input IN is held to a potential less than a threshold voltage of a P type device VTP below VDD. N type device N1 thus remains turned on. When an input transition occurs which causes the input level to exceed a voltage level of (VDD - VTP), device P1 turns off and the gate of device N1 is allowed to bootstrap above voltage VDD. Device D1 ensures that the bootstrap voltage on the gate of device N1 never exceeds the voltage level (VDD + VTN), where VTN is the threshold voltage of an N type device.

Device P2 ensures that the voltage at node OUT reflects the logic level at node IN even during long periods of inactivity with a continuous high voltage level at node IN, by refreshing the gate of device N1 if node OUT ever falls below (VDD - VTP), thus preventing leakage from reducing the N1 gate voltage toward zero.

Disclosed anonymously.

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